Fujitsu Laboratories Ltd. today announced the development of a receiver circuit capable of receiving communications at 56 Gbps. This marks the world's fastest data communications between CPUs equipped in next-generation servers. In recent years, raising data-processing speeds in servers has meant increasing CPU performance, together with boosting the speed of data communications between chips, such as CPUs. However, one obstacle to this has been improving the performance of the circuits that correct degraded waveforms in incoming signals. Fujitsu Laboratories has used a new "look-ahead" architecture in the circuit that compensates for quality degradation in incoming signals, parallelizing the processing and increasing the operating frequency for the circuit in order to double its speed. This technology holds the promise of increasing the performance of next-generation servers and supercomputers.

Details of this technology are being presented at the 2014 Symposia on VLSI Technology and Circuits, opening June 9 in Hawaii (VLSI Circuits Presentation 11-2).

In order to enhance the performance of datacenters underpinning the spread of cloud computing in recent years, a need has arisen for servers that process data faster. While this can be achieved partly through faster CPUs, large-scale systems connecting many CPUs are also being built, and the amount of data transmitted, either within the same CPU-equipped chassis or across separate chassis, is growing dramatically. To cope with these volumes, data communication speeds in the current generation of servers is increasing from a few gigabits per second today to ten or more gigabits per second. Because it is anticipated that data processing volumes will continue to experience explosive growth, however, for the next generation of high-performance servers, the goal is to double current levels to 56 Gbps. Furthermore, the Optical Internetworking Forum (OIF) is moving forward on the standardization of 56 Gbps for the optical modules used for optical transmission between chassis.

Issues

An effective way to speed up the receiver circuit is to improve the processing performance of the decision feedback equalizer (DFE) circuit that compensates for the degraded input-signal waveform (Figure 2).The principle behind DFE is to correct the input signal based on the bit-value of the previous bit and to emphasize changes in the input signal, but the actual circuit design works by choosing between two predefined corrected candidates. If the previous bit value was a 0, the correction process would apply a positive correction to the input signal (additive) to emphasize the change from 0 to 1. If the previous bit value was 1, it would apply a negative correction to the input signal (subtractive) to emphasize the change from 1 to 0. If another 0 was received, the positive compensation would increase the signal level, but not to such a level as would create a problem for the 1/0 decision circuit. In ordinary circuit designs that run at 56 Gbps, there are 16 DFE circuits coupled together. Using 4 DFE circuits as an example, they run at 1/4th the actual frequency. So for 28-Gbps communications rates, 1/4th of that is 142 picoseconds, and four bits-worth of compensation can be applied during that interval. But at 56 Gbps, 1/4th of that speed amounts to 71 picoseconds, during which time only 2 bits-worth of compensation can be applied, resulting in timing errors (Figure 3).

- TAMS SEMICONDUCTOR LIMITED