Japanese researchers at AIST led by Meishoku Masahara have developed a low-resistance source/drain formation technology that can be applied in the finFETs of 14-nm generation and beyond.

The greatest issue for the finFETs of 14-nm generation and beyond was low-resistance source/drain formation on the ultra-thin (10 nm or less) silicon fin. Lower resistance is usually obtained by ion implantation of impurities, but on the fin part, crystal defects that occur during the implantation end up increasing the resistance. Since these crystal defects are difficult to resolve, the result has been that lower resistance is difficult to realize. The heated ion implantation technology developed in the present research is capable of implanting impurity ions in the ultra-thin fin part without causing crystal defects to occur, achieving lower resistance. It has also significantly increased finFET reliability. The developed technology is contributing to the resolution of the issue of low-resistance source/drain formation in the finFETs of 14-nm generation and beyond.

Details of this technology will be presented at the International Electron Device Meeting (IEDM) to be held on December 9 to 11, 2013 in Washington, D.C., USA.

Silicon integrated circuits have realized increasingly advanced performance and integration to date by miniaturizing the transistor elements that are the smallest components of those circuits. The miniaturization of these elements is also linked to cost reduction, and there is intense on-going competition in the development of miniaturized elements. For the technology of 14-nm generation and beyond transistors that are anticipated to enter the market in 2017 and after, however, the greatest issue is the emergence of the influence of source/drain resistance at the ultra-thin fin part. Since increased resistance is a factor in degradation of transistor performance, there is great demand for technology for forming low-resistance source/drain areas.

AIST has been pursuing research and development of the transistors with a new structure called finFETs. In 2003, AIST developed a four-terminal finFET capable of independent gate control and demonstrated its ability to electrically control the threshold voltage (V_th). In 2012, an amorphous metal was used for the gate electrode, instead of the usual polycrystalline metal gate electrode, in order to reduce the variability in V_th. A significant reduction in variability was achieved. Research and development in process technology is presently proceeding with the aim of further improving finFET performance.

- TAMS SEMICONDUCTOR LIMITED